1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, more particularly to node contact application in a semiconductor device.
2. Description of the Prior Art
For some data processing applications, it has become desirable to provide integrated circuit devices that incorporate on the same chip both arrays of memory cells and arrays of high speed logic circuits like those typically used in microprocessors or digital signal processors. It might, for example, be desirable to provide an array of dynamic random access memory cells within the integrated circuit device to provide dedicated, comparatively high speed access to a significant amount of data storage for the logic circuits of the integrated circuit device. Applications that could benefit from the provision of such embedded DRAM include logic circuits that process large amounts of data, such as graphics processors. Use of embedded memory might also reduce the number of pins or input/output terminals required by the integrated circuit device.
Referring to FIG. 1, the merged of logic 10 and DRAM 11 has been widely investigated due to the implemention of system on chip. After gates 14 and bit lines 12 are completed, we form an inter-poly dielectric (IPD) layer 13 by any proper process to isolate the bit lines 12 and the word lines 14 from other overhead devices to prevent the short. Then, to form node contact for lower electrode 21 of a capacitor, photolithography and etch processes are used to form a node contact opening 15 through the dielectric layer 13 to top surface of the substrate 19. Before filling the node contact opening 15 with a conductor, a thin silicon nitride (SiN) layer 20 serving as a buffer is generally formed on inside wall of the node contact opening 15. In conventional, the thin SiN layer 20 was deposited by low pressure chemical vapor deposition (LPCVD). However, the logic PMOS device and salicide stability will be degraded during the LPCVD SiN film 20 deposition. Because the LPCVD process take the time about 4 hours, and its implementing temperature is controlled in the range of about 630 to 780xc2x0 C. However, the logic N/PMOS performance and salicide 16 stability are seriously degraded by the additional DRAM thermal budget. Moreover, the re-diffusion effect 17 in source/drain region 18 occurs during the deposition process for the SiN layer 20. The re-diffusion effect 17 will cause the more leakage of electrons in the source/drain region 18 and lead to the shift of threshold voltage.
For the foregoing reasons, there is a need to develop a method for manufacturing an embedded dynamic random access memory to reduce DRAM process thermal budget and to prevent the shift of threshold voltage due to the re-diffusion effect caused in source/drain region.
In accordance with the present invention, a method is provided for forming an embedded dynamic random access memory. The method substantially prevents the shift of threshold voltage and reduces the thermal budget for manufacturing E-DRAM. In one embodiment, a substrate having a logic region and a memory region is provided. Then, gate structures are formed on both the logic region and the memory region. A first inter-poly dielectric layer is formed on all surfaces, then a opening is formed, over the memory region, from top surface of the first inter-poly dielectric layer to top surface of the substrate. A conductor is formed on the first inter-poly dielectric layer and to fill the opening. Subsequently, a bit line is completed using photolithography and etching the conductor. The next step is forming a second inter-poly dielectric layer on both the first inter-poly dielectric layer and the bit line. Then a node contact opening is formed through the first inter-poly dielectric layer and the second inter-poly dielectric layer to top surface of the substrate. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).